Automatic Discharge Of A Failed Battery

ABSTRACT

A system comprises a battery cell, control logic, and a battery drain latch circuit. The control logic is coupled to the battery cell and determines whether a battery pack has experienced a failure condition. The battery drain latch circuit is activated by the control logic, upon detection of a failure condition, to cause the battery cell to drain energy therefrom.

BACKGROUND

The battery in a battery-operated device (e.g., notebook computer) may,upon occasion, fail. While such failures usually do not pose safetyissues, a failed battery may generate excessive heat or pose otherpotentially undesirable effects.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of exemplary embodiments of the invention,reference will now be made to the accompanying drawings in which:

FIG. 1 shows a system diagram in accordance with various embodiments;

FIG. 2 shows a schematic diagram of a battery pack employing a batterydrain latch circuit in accordance with various embodiments;

FIG. 3 shows a schematic diagram of a battery pack employing a batterydrain latch circuit in accordance with alternative embodiments; and

FIG. 4 shows a method in accordance with various embodiments.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claimsto refer to particular system components. As one skilled in the art willappreciate, computer companies may refer to a component by differentnames. This document does not intend to distinguish between componentsthat differ in name but not function. In the following discussion and inthe claims, the terms “including” and “comprising” are used in anopen-ended fashion, and thus should be interpreted to mean “including,but not limited to . . . .” Also, the term “couple” or “couples” isintended to mean either an indirect, direct, optical or wirelesselectrical connection. Thus, if a first device couples to a seconddevice, that connection may be through a direct electrical connection,through an indirect electrical connection via other devices andconnections, through an optical electrical connection, or through awireless electrical connection. Additionally, the term “system” refersto a collection of two or more hardware and/or software components, andmay be used to refer to an electronic device, such as a computer, aportion of a computer, a combination of computers, etc.

DETAILED DESCRIPTION

FIG. 1 illustrates a host system 10 in accordance with variousembodiments. As shown, host system 10 comprises a processor 12, a memorydevice 14, and possibly other components. Host system 10 may beimplemented as a computer (e.g., a notebook computer) or other type ofbattery-operated device. A battery pack 20 is also shown electricallycoupled to the host system 10 for providing operational power to thehost logic (e.g., processor 12, memory device 14) of the host system 10.The host system 10 thus receives its operating electrical power from thebattery pack 20. The battery pack 20 may be incorporated into, or matedto, the housing of the host system 10 (e.g., internal to the host system10), or may be provided separate from the host system's housing (e.g.,external battery pack). In some embodiments, the battery pack 20 may bereadily removable from the host system such as is typical of manynotebook computers. The battery pack 20 comprises one or more batterycells. That is, the battery pack 20 may comprise a single cell batteryor may comprise a multi-cell pack (e.g., 6-cell, 8-cell pack).

FIG. 2 illustrates an embodiment of the battery pack 20. As shown,battery pack 20 comprises a fuse F1, control logic 22, one or morebattery cells 24, and a battery drain latch circuit 26. The fuse F1 is athree-terminal fuse. One of the terminals receives a control signal 45which causes the fuse to “blow” thereby effectively disconnecting thebattery pack 20 from the host system 10. In the embodiment of FIG. 2, alow logic level for control signal 45 causes the fuse F1 to blow.

In the illustrative embodiment of FIG. 2, the control logic 22 comprisestransistors Q3, Q4, and Q5, a resistor R6, a protection circuit 30(e.g., an integrated circuit (“IC”)), and a microcontroller 32. Themicrocontroller 32 monitors the capacity of the battery cells 24 andprovides a digital interface 33 to the host system 10. Via theinterface, the microcontroller 32 provides data indicative of batterycurrent, voltage, capacity, and other or different data to the hostsystem 10.

Resistor R6 comprises a current sense resistor (e.g., 0.05 ohms), thevoltage across which is proportional to the current to/from the batterycells 24. The protection circuit 30 receives the voltage across resistorR6. The protection circuit 30 is capable of detecting an over-currentcondition via the voltage from the resistor R6. If the voltage acrossresistor R6 is greater than a threshold programmed into the protectioncircuit 30, the protection circuit asserts an output failure signal 40via diode D1. In the illustrative embodiment of FIG. 2, the failuresignal 40 is asserted high to indicate a battery pack failure, althoughin other embodiments, a low value of failure signal 40 may indicate theoccurrence of a failure.

The microcontroller 32 also is capable of detecting one or more batterypack failures such as an over-voltage condition. If the microcontroller32 detects such a failure, the microcontroller also asserts a failuresignal 42 via diode D2. Diodes D1 and D2 effectively “wire OR” thefailure signals 40 and 42 into one failure signal 43 which drives thegate of transistor Q3. If either of the failure signals 40 or 42 areasserted high, transistor Q3 is turned “on” which pulls the controlsignal 45 for fuse F1 low. Forcing control signal 45 low causes the fuseF1 to blow as explained above.

Failure signal 43 is also provided as an input into the battery drainlatch circuit 26. The latch circuit 26 in the illustrative embodiment ofFIG. 2 comprises a two-transistor latch. The two transistors are NPNtransistor Q1 and PNP transistor Q2 as shown. The failure signal 43drives the base of NPN transistor Q1 via resistor R1. Once thetransistor Q1 is turned on, which will be the case when the failuresignal 43 is asserted high to indicate a battery failure mode, currentfrom the battery cells 24 will begin to flow from the battery cells 24through resistors R2 and R3 and through transistor Q1. The voltagedeveloped at node 29 between resistors R2 and R3 drives the base of PNPtransistor Q2. When current flows through resistors R2 and R3, thevoltage at node 29 drops to a point at which PNP transistor Q2 turns on.Once transistor Q2 turns on, current from the battery cells 24 alsobegins to flow through transistor Q2 and resistor R4. In the embodimentof FIG. 2, resistor R4 represents the main battery dissipating componentas most of the battery's energy will be dissipated by resistor R4.

With transistor Q2 on, the voltage at node 31 becomes sufficiently highso as to provide current through resistor R5 back into the base terminalof transistor Q1. The base-driving current through resistor R5 operatesto keep transistor Q1 in an “on” state even if the failure signal 43 isdeasserted by either or both of the protection circuit 30 and/ormicrocontroller 32. The operation of the battery drain latch circuit 26is thus regenerative to keep the latch activated to continue to drainthe battery even following deassertion of the failure signal 43 whichcaused the battery cells 24 to begin to drain in the first place. Thepower dissipated by resistor R4 will decrease over time as the voltageof the battery cells reduces.

FIG. 3 is an alternative embodiment. A difference between the embodimentof FIGS. 2 and 3 is that, while in FIG. 2 the battery drain latchcircuit 26 connects directly to the positive terminal of the batterycells 24, in FIG. 3, the battery drain latch circuit 26 connects to avoltage regulator 34 in the control logic 22. In the illustrativeembodiment of FIG. 3, the voltage regulator 34 comprises a linearregulator implemented in the microcontroller 32. In other embodiments,however, the linear regulator is provided apart from microcontrollersuch as in protection IC 30. The linear regulator 34 generally functionsto provide a regulated output voltage (e.g., 3.3 VDC). The regulatedoutput voltage from the linear regulator 34 is used to provide thebattery-draining current in the embodiment of FIG. 3. Thus, the batterycells 24 power the microcontroller 32 and the linear regulator 34 in themicrocontroller begins to provide current (generated by the batterycells) into the battery drain latch circuit 26. Because the linearregulator 34 provides a relatively constant output voltage, the currentdrawn from the battery cells 24 in FIG. 3 is relatively constant, as isthe power dissipation of resistor R3. In the embodiment of FIG. 3,energy is dissipated in both linear regulator 34 and resistor R4.

FIG. 4 illustrates a method 50 in accordance with various embodiments.As shown, method 50 comprises detecting a failure of the battery pack(52). As a result of detecting a failure, the method further comprisesautomatically causing the battery pack to discharge its energy (54).

In some embodiments, all of the battery pack's energy stored in cells 24is discharged. In other embodiments, most (e.g., more than 95%) of thecells' energy is discharged. In various embodiments, at least enoughenergy is discharged from the battery pack 20 to render the packgenerally incapable of producing any undesirable problems while in thefailure mode.

For the embodiments described herein, the battery pack 20 will take afinite amount of time to drain from a fully charged state, but generallyless time than would occur without the implementation of the techniquesdescribed herein. In some embodiments, the battery pack 20 may take afew hours, a few days, or a week to drain.

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present invention. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

1. A system, comprising: a battery cell; control logic coupled to thebattery cell, said control logic determines whether a battery pack hasexperienced a failure condition; and a battery drain latch circuit thatis activated by said control logic, upon detection of a failurecondition, to cause said battery cell to drain energy.
 2. The system ofclaim 1 wherein said battery drain latch circuit comprises atwo-transistor latch.
 3. The system of claim 1 wherein said batterydrain latch circuit receives an input failure signal from said controllogic, said failure signal indicating an occurrence of a failurecondition.
 4. The system of claim 1 wherein said battery drain latchcircuit continues to cause energy to be drained from said battery celleven upon a deassertion of the failure signal.
 5. The system of claim 1wherein said battery drain latch circuit is electrically connected to aterminal of the battery cell.
 6. The system of claim 1 wherein saidcontrol logic comprises a voltage regulator that provides a regulatedvoltage from said control logic, and wherein the battery drain latchcircuit is electrically connected to a terminal of the voltageregulator.
 7. The system of claim 1 wherein said battery drain latchcircuit causes said battery cell to drain all of said energy in saidcell, or all but 1% or less of said energy in said cell.
 8. The systemof claim 1 wherein said battery drain latch circuit comprises a resistorthat dissipates energy drained from said battery cell.
 9. The system ofclaim 1 further comprising host logic that receives operational powerfrom said battery cell.
 10. A system, comprising: means for detecting afailure condition of a battery pack; means for, as a result of detectingthe failure condition, automatically causing the battery pack todissipate energy contained therein.
 11. The system of claim 10 whereinthe means for automatically causing the battery pack to dissipate isalso for activating a latch.
 12. The system of claim 11 wherein themeans for automatically causing the battery pack to dissipate is alsofor dissipating energy through a resistor.
 13. The system of claim 10wherein the means for automatically causing the battery pack todissipate is also for dissipating energy from a voltage regulator in thebattery pack.
 14. A method, comprising: detecting a failure condition ofa battery pack; as a result of detecting the failure condition,asserting a failure signal to a latch; and the latch causing energy toautomatically be drained from the battery pack.
 15. The method of claim14 further comprising the latch continuing to cause the battery pack tocontinue to be drained upon deassertion of the failure signal.
 16. Themethod of claim 15 wherein the latch causing energy to automatically bedrained from the battery pack comprises dissipating energy through aresistor in the latch.
 17. The method of claim 15 wherein the latchcausing energy to automatically be drained from the battery packcomprises dissipating energy from a voltage regulator in said batterypack.